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[ARM Disassembler] Flawed display of ALU instructions with a register shift #2349

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lunasorcery opened this issue Nov 9, 2021 · 0 comments
Closed

[ARM Disassembler] Flawed display of ALU instructions with a register shift #2349

lunasorcery opened this issue Nov 9, 2021 · 0 comments

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@lunasorcery
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Observed at 0.9.2 (f6d5f51)

For ALU operations (and, bic, etc), the disassembler erroneously omits the lsl when the second operand is left-shifted by r0.

Given the following assembly:

and r3, r3, r2, lsl #0  ; opcode E0033002
and r3, r3, r2, lsl #1  ; opcode E0033082
and r3, r3, r2, lsl r0  ; opcode E0033012
and r3, r3, r2, lsl r1  ; opcode E0033112

mGBA will disassemble as:

and r3, r3, r2          ; zero-shift omitted, as expected
and r3, r3, r2, lsl #1
and r3, r3, r2, r0      ; `lsl` suspiciously missing
and r3, r3, r2, lsl r1
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